1. Field of the Invention
This invention relates to clock generation. In particular, the invention relates to the control of duty cycle of the clock signal.
2. Description of Related Art
Clock signals are basic elements in digital circuits. A clock signal may be used to trigger flip-flops, serve as a timing reference, provide data and address strobing, and perform many other timing and control functions. Since a clock signal may be connected to a number of circuit elements, it is usually buffered to increase the driving capability.
A clock signal may be generated by a number of methods including use of a phase-lock loop (PLL). It is desirable that the duty cycle of the clock signal to be approximately 50%. To distribute the clock signal to various circuit elements, a clock distribution circuit is used. The clock distribution circuit usually uses inverters or buffers. Variations in the P and N devices of the distribution inverters or clock skew due to buffers tend to distort the duty cycle.
Existing techniques to maintain a balanced duty cycle of 50% include using manual control of current sources. These techniques have a number of drawbacks. First, as processes scale down and supply voltage decreases, the headroom used by the series current sources significantly decreases the range of control. Second, there is non-linearity at the ends of the control range.